`timescale 1ps/1ps
`define clock_period 10

module top_module ( );

    reg	clk;
    
    dut u_dut_0(
        .clk(clk)
    );
    
    always #(`clock_period / 2) clk = ~clk;
    
    initial begin
        clk = 1'b0;
    end
    
endmodule
